The present invention is directed to a communication link interface between two hardware systems in which different clock rates are tolerated. In particular, the present invention permits a 2 to 1 data rate tolerance.
It has been the conventional practice in communicating between hardware systems to provide an intermediate clock rate usually common to neither the sending nor the receiving hardware system. Examples of this practice are Ethernet and other local area networks, T1 and other digital telephony systems.
It is an object of the present invention to connect two hardware systems without the use of an intermediate clock rate. This has the advantage of requiring less hardware, mostly for the reason that there is one less synchronization operation required. It is a further object of the present invention to connect two systems operating at their own different clock rates.